This invention relates to a dynamic semiconductor memory device with banks capable of operating independently which is applied to high-speed data transfer DRAMs (dynamic random access memories), such as synchronous DRAMs, Rambus DRAMs, and SynchLink DRAMs, which have appeared after 64-Mbit DRAMs.
It was the 16-Mbit synchronous DRAM that first used the concept of bank. FIG. 42 shows a conventional synchronous DRAM. In the synchronous DRAM, two large memory cell arrays M0, M1 are provided in a chip CP. These memory cell arrays M0, M1 are used as bank BK0, BK1 respectively. In the middle of each of the memory cell arrays M0, M1, a shared row decoder (SRDC) and a word line drive circuit (WLD) are provided. On both sides of the shared row decoder and word line drive circuit, memory blocks MBLKs are provided. Shared sense amplifiers (SS/A) shared by adjacent memory blocks are provided between the memory blocks MBLKs. Each of the memory cell arrays M0, M1 is provided with a column decoder (CDC). A peripheral circuit is provided between the column decoders. In the case of such a configuration, it is relatively easy to arrange the individual circuits. In the figures that follow, the same parts as those in FIG. 42 are indicated by the same reference symbols.
FIG. 43 shows the bank structure of a 64-Mbit synchronous DRAM. The DRAM has four banks, BK0, BK1, BK2, and BK3. In the structure, an area in which memory cell arrays are arranged in a chip is divided into four pieces. A bank is set for each area. Therefore, banks can be allocated readily to the individual memory cell arrays.
FIG. 44 shows the bank structure of a 256-Mbit synchronous DRAM. In the DRAM, a structure of eight banks, larger than the number of divisions of memory cell array, is considered to be standard. The allocation of pins is standardized as shown in FIG. 45. A set of eight I/O pins for inputting and outputting data is arranged on each side of one longitudinal end of the package and another set of eight I/O pins is arranged on each side of the other longitudinal end of the package; and a set of pins for inputting commands, including a row and address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE, and address signals Add is arranged on each side of the middle of the package. In the layout, banks of the same structure are allocated symmetrically with respect to the center line of the chip.
Specifically, in FIG. 44, an area in which memory cell arrays are arranged is divided in two equal parts. In the middle of the chip CP, a peripheral circuit 341 is provided longitudinally. In the area above the peripheral circuit 341, bank BK0 to bank BK7 are arranged in that order from left to right. In the area below the peripheral circuit 341, bank BK0 to bank BK7 are arranged in that order from right to left. With this structure, because memory blocks of the same banks are not arranged adjacently along the peripheral circuit 341, shared row decoders cannot be used. To access each bank independently, a row decoder RDC and a word line drive circuit (not shown) are provided on each side of each bank. This causes a problem: two row decoders and two word line drive circuits must be provided for adjacent banks, which requires a large area for their arrangement.
FIG. 46 shows the bank structure of a synchronous DRAM. As shown in FIG. 46, a method of allocating banks in the direction in which sense amplifiers are provided has been considered. With this structure, because memory blocks of the same banks are arranged adjacently along the peripheral circuit 341, shared row decoders SRDC can be used. At the boundaries of banks, however, shared row decoders SRDC cannot be used, two sense amplifiers S/A used for each bank must be provided at the boundaries (represented by bold lines) of the banks. As a result, a large area for providing sense amplifiers at the boundaries of the banks is needed, which makes the chip size larger in the direction in which banks are arranged.
When banks are allocated as shown in FIG. 46, a disadvantage results in that the efficiency of remedying defective rows by a flexible redundancy method decreases. The flexible redundancy method is a method of providing redundancy word lines for cell arrays.
FIG. 47A shows the flexible redundancy method applied to cell arrays to which conventional banks have not been allocated. The memory cell array represents a 16-Mbit memory cell array in which sixteen 1-Mbit cell arrays CAs are arranged. Shared sense amplifiers SS/As are provided between cell arrays CAs. Near a column decoder CDC, a redundancy cell array R/D with redundancy word lines is provided exclusively for redundancy. The redundancy cell array R/D has a capacity of, for example, about 128 Kbits. A sense amplifier S/A is provided on each side of the redundancy cell array R/D.
As described above, because one redundancy cell array R/D is provided for 16 cell arrays CAs, even if any one of the 16 cell arrays has a defective word line, the defective word line can be replaced with a redundancy word line in the redundancy cell array R/D. When such a flexible redundancy method is compared with a method of providing a redundancy word line for every 1 Mbits, the flexible redundancy method has an improved efficiency of remedying defective word lines as compared with the latter method, provided that the total number of redundancy word lines in the former method is the same as that of the latter method. For example, the total number of redundancy word lines in a case where a single redundancy word line is provided for every 1 Mbits is equal to that in a case where 16 word lines are provided for a total of 16 Mbits. When a single redundancy word line is provided for every 1 Mbits, however, if more than one failure occurs in a set of 1 Mbits, they cannot be remedied, whereas when 16 word lines are provided for a total of 16 Mbits, they can be remedied.
When banks are arranged as shown in FIG. 46, a redundancy cell array R/D must be provided for each bank to enable each bank to operate independently. Specifically, when the flexible redundancy method is applied to the structure of FIG. 46, four redundancy cell arrays R/Ds corresponding to the individual banks must be provided for the 16 cell arrays that are selected by a single column decoder, as shown in FIG. 47B. With this structure, because a sense amplifier is provided on each side of each redundancy cell array R/D, even when the total number of redundancy word lines is the same as that in FIG. 47A, the area for sense amplifiers can increase, resulting in an increase in the chip size.
As described above, when the number of banks provided in a chip is larger than the number of divisions of memory cell arrays, it is expected that it will be difficult to use shared row decoders, shared sense amplifiers, and flexible redundancy method effectively and therefore the chip size will increase.